View CAT6095VP2GT_8663601.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2011 may, 2011 ? rev. 5 1 publication order number: cat6095/d cat6095 digital output temperature sensor description the cat6095 is a jedec jc42.4 compliant temperature sensor designed for general purpose temperature measurements requiring a digital output. the cat6095 measures temperature at least 10 times every second. temperature readings can be retrieved by the host via the serial interface, and are compared to high, low and critical trigger limits stored into internal registers. over or under limit conditions can be signaled on the open ? drain event pin. the cat6095 is packaged in space saving tdfn package with exposed backside die attach pads (dap). the exposed dap reduces overall thermal resistance, thus providing faster response to thermal changes when compared to soic, tssop or sot packages. features ? jedec jc42.4 compliant temperature sensor ? temperature range: ? 40 c to +125 c ? supply range: 3.3 v 10% ? i 2 c / smbus interface ? schmitt triggers and noise suppression filters on scl and sda inputs ? low power cmos technology ? 2 x 3 x 0.75 mm tdfn package ? these devices are pb ? free and are rohs compliant figure 1. functional symbol sda scl cat6095 v cc v ss a 2 , a 1 , a 0 event http://onsemi.com pin configuration sda event v cc v ss a 2 a 1 a 0 1 see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information scl (top view) device address input a 0 , a 1 , a 2 serial data input/output sda serial clock input scl open ? drain event output event power supply v cc ground v ss function pin name pin functions for the location of pin 1, please consult the corresponding package drawing. tdfn ? 8 vp2 suffix case 511ak backside exposed dap at v ss dap marking diagram hmc all ym hmc = specific device code a = assembly location code ll = assembly lot number (last two digits) y = production year (last digit) m = production month (1 ? 9, o, n, d) = pb ? free package
cat6095 http://onsemi.com 2 table 1. absolute maximum ratings parameter rating units operating temperature ? 45 to +130 c storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. the a 0 pin can be raised to a hv level compatible with the use of a ddr3 spd device sharing the bus with the ts. scl and sda inputs can be raised to the maximum limit, irrespect ive of v cc . table 2. temperature characteristics (v cc = 3.3 v 10%, t a = ? 40 c to +125 c, unless otherwise specified) parameter test conditions/comments max unit temperature reading error class b, jc42.4 compliant +75 c t a +95 c, active range 1.0 c +40 c t a +125 c, monitor range 2.0 c ? 20 c t a +125 c, sensing range 3.0 c adc resolution 12 bits temperature resolution 0.0625 c temperature conversion time 100 ms thermal resistance (note 2) ja junction ? to ? ambient (still air) 92 c/w 2. power dissipation is defined as p j = (t j ? t a )/ ja , where t j is the junction temperature and t a is the ambient temperature. the thermal resistance value refers to the case of a package being used on a standard 2 ? layer pcb. table 3. d.c. operating characteristics (v cc = 3.3 v 10%, t a = ? 40 c to +125 c, unless otherwise specified) symbol parameter test conditions/comments min max unit i cc supply current ts active 200 a i shdn ts shut ? down; no bus activity 10 a i l i/o pin leakage current pin at gnd or v cc 2 a v il input low voltage ? 0.5 0.3 x v cc v v ih input high voltage 0.7 x v cc v cc + 0.5 v v ol output low voltage i ol = 3 ma, v cc > 2.5 v 0.4 v
cat6095 http://onsemi.com 3 table 4. a.c. characteristics (v cc = 3.3 v 10%, t a = ? 40 c to +125 c) (note 3) symbol parameter min max units f scl (note 4) clock frequency 10 400 khz t high high period of scl clock 600 ns t low low period of scl clock 1300 ns t timeout (note 4) smbus scl clock low timeout 25 35 ms t r (note 5) sda and scl rise time 300 ns t f (note 5) sda and scl fall time 300 ns t su:dat (note 6) data setup time 100 ns t hd:dat (note 5) data hold time (for input data) 0 ns data hold time (for output data) 300 900 ns t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:sto stop condition setup time 600 ns t buf bus free time between stop and start 1300 ns t i noise pulse filtered at scl and sda inputs 100 ns t pu (note 7) power ? up delay to valid temperature recording 100 ms 3. timing reference points are set at 30%, respectively 70% of v cc , as illustrated in figure 11. bus loading must be such as to allow meeting the v il , v ol as well as the various timing limits. 4. the ts interface will reset itself and will release the sda line if the scl line stays low beyond the t timeout limit. the time ? out count is started (and then re ? started) on every negative transition of scl in the time interval between start and stop. 5. in a ?wired ? or? system (such as i 2 c or smbus), sda rise time is determined by bus loading. since each bus pull ? down device must be able to sink the (external) bus pull ? up current (in order to meet the v il and/or v ol limits), it follows that sda fall time is inherently faster than sda rise time. sda rise time can exceed the standard recommended t r limit, as long as it does not exceed t low ? t hd:dat ? t su:dat , where t low and t hd:dat are actual values (rather than spec limits). a shorter t hd:dat leaves more room for a longer sda t r , allowing for a more capacitive bus or a larger bus pull ? up resistor. at the minimum t low spec limit of 1300 ns, the maximum t hd:dat of 900 ns demands a maximum sda t r of 300 ns. the cat6095?s maximum t hd:dat is <700 ns, thus allowing for an sda t r of up to 500 ns at minimum t low . 6. the minimum t su:dat of 100 ns is a limit recommended by standards. the ts will accept a t su:dat of 0 ns. 7. the first valid temperature recording can be expected after t pu at nominal supply voltage. table 5. pin capacitance (t a = 25 c, v cc = 3.3 v, f = 1 mhz) symbol parameter test conditions/comments min max unit c in sda, event pin capacitance v in = 0 8 pf input capacitance (other pins) v in = 0 6 pf
cat6095 http://onsemi.com 4 typical performance characteristics (v cc = 3.3 v, t a = ? 25 c to +125 c, unless otherwise specified.) figure 2. active current (i 2 c ? bus idle) figure 3. standby current (i 2 c ? bus idle, ts shut ? down) t amb ( c) t amb ( c) 125 100 75 50 25 0 ? 25 0 50 100 150 200 250 300 100 75 50 25 0 ? 25 ? 1 1 2 3 4 5 figure 4. temperature read ? out error figure 5. a/d conversion time t amb ( c) t amb ( c) 125 100 75 50 25 0 ? 25 ? 4 ? 2 0 2 4 125 100 75 50 25 0 ? 25 20 30 40 60 70 80 figure 6. por threshold voltage figure 7. smbus scl clock low timeout t amb ( c) t amb ( c) 125 100 75 50 25 0 ? 25 1.0 1.4 1.8 2.2 2.6 3.0 125 100 75 50 25 0 ? 25 20 25 30 35 40 i cc ( a) i shdn ( a) t ( c) t conv (ms) v th (v) t timeout (ms) 125 50 part # 1 part # 2 0 ? 3 ? 1 1 3
cat6095 http://onsemi.com 5 pin description scl: the serial clock input pin accepts the serial clock generated by the master (host). sda: the serial data i/o pin receives input data and transmits data stored in the internal registers. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a0, a1 and a2: the address pins set the device address. these pins have on ? chip pull ? down resistors. event : the open ? drain event pin can be programmed to signal over/under temperature limit conditions. power ? on reset the cat6095 incorporates power ? on reset (por) circuitry which monitors the supply voltage, and then resets (initializes) the internal state machine below a por trigger level of approximately 2.0 v, i.e. well below the minimum recommended v cc value. the temperature sensor (ts) powers-up into conversion mode. the internal state machine will operate properly above the por trigger level, but valid temperature readings can be expected only after the first conversion cycle started and completed at nominal supply voltage. device interface the cat6095 supports i 2 c and smbus data transmission protocols. these protocols describe serial communication between transmitters and receivers sharing a 2 ? wire data bus. data ow is controlled by a master device, which generates the serial clock and the start and stop conditions. the ca t6095 acts as a slave device. master and slave alternate as transmitter and receiver. up to 8 ca t6095 devices may be present on the bus simultaneously, and can be individually addressed by matching the logic state of the address inputs a0, a1, and a2. i 2 c/smbus protocol the i 2 c/smbus uses two ?wires?, one for clock (scl) and one for data (sda). the two wires are connected to the v cc supply via pull ? up resistors. master and slave devices connect to the bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interpreted as a start or stop condition (figure 8). start the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake ? up? call to all slaves. absent a start, a slave will not respond to commands. stop the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. the stop tells the slave that no more data will be written to or read from the slave. device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8 ? bit serial slave address. the first 4 bits of the slave address (the preamble) select the temperature sensor (ts preamble = 0011) as shown in figure 9. the next 3 bits, a2, a1 and a0, select one of 8 possible ts slave devices. the last bit, r/w , speci es whether a read (1) or write (0) operation is being performed. acknowledge a matching slave address is acknowledged (ack) by the slave by pulling down the sda line during the 9 th clock cycle (figure 10). after that, the slave will acknowledge all data bytes sent to the bus by the master. when the slave is the transmitter, the master will in turn acknowledge data bytes in the 9 th clock cycle. the slave will stop transmitting after the master does not respond with acknowledge (noack) and then issues a stop. bus timing is illustrated in figure 11.
cat6095 http://onsemi.com 6 figure 8. start/stop timing start bit sda stop bit scl figure 9. slave address bits temperature sensor 0011 device address preamble figure 10. acknowledge timing acknowledge 1 start scl from master 89 data output from transmitter data output from receiver 30% 30% 70% 30% 70% 30% 30% 70% 70% 70% 70% 70% 70% scl sda figure 11. bus timing a 2 a 1 a 0 r/w t buf t su:sto t f t su:sta t hd:sta t hd:dat t su:dat t r t low t high
cat6095 http://onsemi.com 7 write operations temperature sensor register write to write data to a ts register the master creates a start condition on the bus, and then sends out the appropriate slave address (with the r/w bit set to ?0?), followed by an address byte and two data bytes. the matching slave will acknowledge the slave address, ts register address and the ts register data (figure 12). the master then ends the session by creating a stop condition on the bus. the stop completes the ts register update. note that all registers in the ts are ?volatile? meaning any data contained in them is lost when power is removed from the chip. read operations immediate read upon power-up, the temperature sensor (ts) address counter is initialized to 00h. the ts address counter will thus point to the capability register. this address counter may be updated by subsequent operations. a cat6095 presented with a slave address containing a ?1? in the r/w position will acknowledge the slave address and will then start transmitting data being pointed at by the current ts register address counter. the master stops this transmission by responding with noack, followed by a stop (figure 13). selective read the read operation can be started at an address dif ferent from the one stored in the address counter, by preceding the immediate read sequence with a ?data less? w rite operation. the master sends out a start, slave address and address byte, but rather than following up with data (as in a write operation), the master then issues another start and continuous with an immediate read sequence (figure 14). figure 12. temperature sensor register write slave register address address s a c k bus activity: master sda line slave s t a r t a c k data (msb) data (lsb) a c k a c k a c k a c k p s t o p figure 13. immediate read data (msb) data (lsb) n o a c k slave address bus activity: master sda line slave a c k a c k s s t a r t a c k p s t o p figure 14. selective read bus activity: master slave address sda line data (msb) slave slave data (lsb) register address address s s t a r t a c k a c k a c k s s t a r t a c k n o a c k s t o p p
cat6095 http://onsemi.com 8 temperature sensor operation the cat6095 temperature sensor (ts) combines a proportional to absolute temperature (ptat) sensor with a ? modulator, yielding a 12 bit plus sign digital temperature representation. the ts runs on an internal clock, and starts a new conversion cycle at least every 100 ms. the result of the most recent conversion is stored in the temperature data register (tdr) , and remains there following a ts shut ? down. reading from the tdr does not interfere with the conversion cycle. the value stored in the tdr is compared against limits stored in the high limit register (hlr), the low limit register (llr) and/or critical temperature register (ctr) . if the measured value is outside the alarm limits or above the critical limit, then the event pin may be asserted. the event output function is programmable, via the configuration register for interrupt mode, comparator mode and polarity. the temperature limit registers can be read or written by the host, via the serial interface. at power ? on, all the (writable) internal registers default to 0x0000, and should therefore be initialized by the host to the desired values. the event output starts out disabled (corresponding to polarity active low); thus preventing irrelevant event bus activity before the limit registers are initialized. while the ts is enabled (not shut ? down), event conditions are normally generated by a change in measured temperature as recorded in the tdr, but limit changes can also trigger events as soon as the new limit creates an event condition, i.e. asynchronously with the temperature sampling activity. in order to minimize the thermal resistance between sensor and pcb, it is recommended that the exposed backside die attach pad (dap) be soldered to the pcb ground plane. registers the cat6095 contains eight 16 ? bit wide registers allocated to ts functions, as shown in table 6. upon power ? up, the internal address counter points to the capability register. capability register (user read only) this register lists the capabilities of the ts, as detailed in the corresponding bit map. configuration register (read/write) this register controls the various operating modes of the ts, as detailed in the corresponding bit map. temperature trip point registers (read/write) the cat6095 features 3 temperature limit registers, the hlr , llr and clr mentioned earlier. the temperature value recorded in the tdr is compared to the various limit values, and the result is used to activate the event pin. to avoid undesirable event pin activity, this pin is automatically disabled at power ? up to allow the host to initialize the limit registers and the converter to complete the first conversion cycle under nominal supply conditions. data format is two? s complement with the lsb representing 0.25 c, as detailed in the corresponding bit maps. temperature data register (user read only) this register stores the measured temperature, as well as trip status information. b15, b14 and b13 are the trip status bits, representing the relationship between measured temperature and the 3 limit values; these bits are not af fected by event status or by configuration register settings. measured temperature is represented by bits b12 to b0. data format is two?s complement, where b12 represents the sign, b11 represents 128 c, etc. and b0 represents 0.0625 c. manufacturer id register (read only) the manufacturer id assigned by the pci ? sig trade organization to the cat6095 device is 0x1b09. device id and revision register (read only) this register contains manufacturer specific device id and device revision information.
cat6095 http://onsemi.com 9 table 6. temperature sensor registers register address register name power ? on default read/write 0x00 capability register 0x007f read 0x01 configuration register 0x0000 read/write 0x02 high limit register 0x0000 read/write 0x03 low limit register 0x0000 read/write 0x04 critical limit register 0x0000 read/write 0x05 temperature data register undefined read 0x06 manufacturer id register 0x1b09 read 0x07 device id/revision register 0x0813 read 0x08 ? reserved ? ? table 7. capability register b15 b14 b13 b12 b11 b10 b9 b8 rfu rfu rfu rfu rfu rfu rfu rfu b7 b6 b5 b4 b3 b2 b1 b0 evsd tmout rfu tres [1:0] range acc event bit description b15:b8 reserved for future use; can not be written; should be ignored; will typically read as 0 b7 (note 8) 0: configuration register bit 4 is frozen upon setting configuration register bit 8 (i.e. a ts shut ? down freezes the event output) 1: configuration register bit 4 is cleared upon setting configuration register bit 8 (i.e. a ts shut ? down de ? asserts the event output) b6 0: the ts implements smbus time ? out within the range 10 to 60 ms 1: the ts implements smbus time ? out within the range 25 to 35 ms b5 0: pin a 0 v hv compliance required for rswp/spd compatibility not explicitly stated 1: pin a 0 v hv compliance required for rswp/spd compatibility explicitly stated b4:b3 00: lsb = 0.50 c (9 bit resolution) 01: lsb = 0.25 c (10 bit) 10: lsb = 0.125 c (11 bit) 11: lsb = 0.0625 c (12 bit) b2 0: positive temperature only 1: positive and negative temperature b1 0: 2 c over the active range and 3 c over the operating range (class c) 1: 1 c over the active range and 2 c over the monitor range (class b) b0 0: critical temperature only 1: alarm and critical temperature 8. configuration register bit 4 can be cleared (but not set) after configuration register bit 8 is set, by writing a ?1? to conf iguration register bit 5 (i.e. the event output can be de-asserted during ts shut-down periods)
cat6095 http://onsemi.com 10 table 8. configuration register b15 b14 b13 b12 b11 b10 b9 b8 rfu rfu rfu rfu rfu hyst [1:0] shdn b7 b6 b5 b4 b3 b2 b1 b0 tcrit_lock event_lock clear event_sts event_ctrl tcrit_only event_pol event_mode bit description b15:b11 reserved for future use; can not be written; should be ignored; will typically read as 0 b10:b9 (note 9) 00: disable hysteresis 01: set hysteresis at 1.5 c 10: set hysteresis at 3 c 11: set hysteresis at 6 c b8 (note 13) 0: thermal sensor is enabled; temperature readings are updated at sampling rate 1: thermal sensor is shut down; temperature reading is frozen to value recorded before shdn b7 (note 12) 0: critical trip register can be updated 1: critical trip register cannot be modified; this bit can be cleared only at por b6 (note 12) 0: alarm trip registers can be updated 1: alarm trip registers cannot be modified; this bit can be cleared only at por b5 (note 11) 0: always reads as 0 (self ? clearing) 1: writing a 1 to this position clears an event recording in interrupt mode only b4 (note 10) 0: event output pin is not being asserted 1: event output pin is being asserted b3 (note 9) 0: event output disabled; polarity dependent : open ? drain for bit b1 = 0 and grounded for b1 = 1 1: event output enabled b2 (note 15) 0: event condition triggered by alarm or critical temperature limit crossing 1: event condition triggered by critical temperature limit crossing only b1 (notes 9, 14) 0: event output active low 1: event output active high b0 (note 9) 0: comparator mode 1: interrupt mode 9. can not be altered (set or cleared) as long as either one of the two lock bits, b6 or b7 is set. 10. this bit is a polarity independent ?software? copy of the event pin, i.e. it is under the control of b3. 11. writing a ?1? to this bit clears an event condition in interrupt mode, but has no effect in comparator mode. when read, this bit always r eturns 0. once the measured temperature exceeds the critical limit, setting this bit has no effect (see figure 12). 12. cleared at power-on reset (por). once set, this bit can only be cleared by a por condition. 13. the ts powers up into active mode, i.e. this bit is cleared at power-on reset (por). when the ts is shut down the adc is dis abled and the temperature reading is frozen to the most recently recorded value. the ts can not be shut down (b8 can not be set) as long as e ither one of the two lock bits, b6 or b7 is set. however, the bit can be cleared at any time. 14. the event output is ?open-drain? and requires an external pull-up resistor for either polarity. the ?natural? polarity is ?active low?, as it allows ?wired-or? operation on the event bus. 15. can not be set as long as lock bit b6 is set.
cat6095 http://onsemi.com 11 table 9. high limit register b15 b14 b13 b12 b11 b10 b9 b8 0 0 0 sign 128 c 64 c 32 c 16 c b7 b6 b5 b4 b3 b2 b1 b0 8 c 4 c 2 c 1 c 0.5 c 0.25 c 0 0 table 10. low limit register b15 b14 b13 b12 b11 b10 b9 b8 0 0 0 sign 128 c 64 c 32 c 16 c b7 b6 b5 b4 b3 b2 b1 b0 8 c 4 c 2 c 1 c 0.5 c 0.25 c 0 0 table 11. tcrit limit register b15 b14 b13 b12 b11 b10 b9 b8 0 0 0 sign 128 c 64 c 32 c 16 c b7 b6 b5 b4 b3 b2 b1 b0 8 c 4 c 2 c 1 c 0.5 c 0.25 c 0 0 table 12. temperature data register b15 b14 b13 b12 b11 b10 b9 b8 tcrit high low sign 128 c 64 c 32 c 16 c b7 b6 b5 b4 b3 b2 b1 b0 8 c 4 c 2 c 1 c 0.5 c 0.25 c (note 16) 0.125 c (note 16) 0.0625 c (note 16) 16. when applicable (as defined by capability bit tres), unsupported bits will read as 0 bit description b15 0: temperature is below the tcrit limit 1: temperature is equal to or above the tcrit limit b14 0: temperature is equal to or below the high limit 1: temperature is above the high limit b13 0: temperature is equal to or above the low limit 1: temperature is below the low limit
cat6095 http://onsemi.com 12 register data format the values used in the temperature data register and the 3 temperature trip point registers are expressed in two?s complement format. the measured temperature value is expressed with 12 ? bit resolution, while the 3 trip temperature limits are set with 10 ? bit resolution. the total temperature range is arbitrarily defined as 256 c, thus yielding an lsb of 0.0625 c for the measured temperature and 0.25 c for the 3 limit values. bit b12 in all temperature registers represents the sign, with a ?0? indicating a positive, and a ?1? a negative value. in two?s complement format, negative values are obtained by complementing their positive counterpart and adding a ?1?, so that the sum of opposite signed numbers, but of equal absolute value, adds up to zero. note that trailing ?0? bits, are ?0? irrespective of polarity. therefore the don?t care bits (b1 and b0) in the 10 ? bit resolution temperature limit registers, are always ?0?. table 13. 12 ? bit temperature data format binary (b12 to b0) hex temperature 1 1100 1001 0000 1c90 ? 55 c 1 1100 1110 0000 1ce0 ? 50 c 1 1110 0111 0000 1e70 ? 25 c 1 1111 1111 1111 1fff ? 0.0625 c 0 0000 0000 0000 000 0 c 0 0000 0000 0001 001 +0.0625 c 0 0001 1001 0000 190 +25 c 0 0011 0010 0000 320 +50 c 0 0111 1101 0000 7d0 +125 c event pin functionality the event output reacts to temperature changes as illustrated in figure 15, and according to the operating mode defined by the configuration register. in interrupt mode , the enabled event output will be asserted every time the temperature crosses one of the alarm window limits, and can be de ? asserted by writing a ?1? to the clear event bit (b5) in the configuration register. when the temperature exceeds the critical limit, the event remains asserted as long as the temperature stays above the critical limit and can not be cleared. in comparator mode , the event output is asserted outside the alarm window limits, while in critical temperature mode , event is asserted only above the critical limit. the exact trip limits are determined by the 3 temperature limit settings and the hysteresis offsets, as illustrated in figure 16. following a ts shut ? down request, the converter is stopped and the most recently recorded temperature value present in the tdr is frozen; the event output will continue to reflect the state immediately preceding the shut ? down command. therefore, if the state of the event output creates an undesirable bus condition, appropriate action must be taken either before or after shutting down the ts. this may require clearing the event, disabling the event output or perhaps changing the event output polarity. in normal use, events are triggered by a change in recorded temperature, but the ca t6095 will also respond to limit register changes. whereas recorded temperature values a re updated at sampling rate frequency, limits can be modified at any time. the enabled event output will react to limit changes as soon as the respective registers are updated. this feature may be useful during testing.
cat6095 http://onsemi.com 13 figure 15. event detail alarm window critical upper lower temperature hysteresis affects these trip points software clears event time event in ?interrupt? event in ?comparator? mode event in ?critical temp only? mode *event cannot be cleared once the dut temperature is greater than the critical tem perature figure 16. hysteresis detail below window bit above window bit t l t h t l ? hyst t h ? hyst
cat6095 http://onsemi.com 14 package dimensions tdfn8, 2x3 case 511ak ? 01 issue a pin#1 identification e2 e a3 eb d a2 top view side view bottom view pin#1 index area front view a1 a l d2 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.30 1.40 1.50 e 3.00 e2 1.20 1.30 1.40 e 2.90 0.50 typ 3.10 l 0.20 0.30 0.40 a2 0.45 0.55 0.65
cat6095 http://onsemi.com 15 example of ordering information prefix device # suffix company id cat 6095 vp2 product number 6095 gt4 package vp2: tdfn t: tape & reel 4: 4,000/reel lead finish g: nipdau tape & reel (note 21) 17. all packages are rohs ? compliant (lead ? free, halogen ? free) 18. the standard lead finish is nipdau. 19. this device used in the above example is a cat6095, in tdfn, nipdau lead frame, tape & reel, 4,000/reel. 20. for additional package and temperature options, please contact your nearest on semiconductor sales office. 21. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat6095/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of CAT6095VP2GT

	To Download CAT6095VP2GT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .